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1 features ? 64-megabit (4m x 16) flash memory 2.7v - 3.6v read/write high performance C asynchronous access time C 70 ns C page mode read time C 20 ns sector erase architecture C eight 4k word sectors with individual write lockout C 32k word main sectors with individual write lockout typical sector erase time: 32k word sectors C 500 ms; 4k word sectors C 100 ms suspend/resume feature for erase and program C supports reading and programming data from any sector by suspending erase of a different sector C supports reading any word by suspending programming of any other word low-power operation C30 ma active C 10 a standby 1.8v i/o option reduces overall system power data polling and toggle bit for end of program detection vpp pin for write protection and accelerated program/erase operations reset input for device initialization tsop or cbga package top or bottom boot block configuration available 128-bit protection register common flash interface (cfi) description the at49bv640(t) is a 2.7-volt 64-megabit flash memory. the memory is divided into multiple sectors for erase operations. the device can be read or reprogrammed off a single 2.7v power supply, making it ideally suited for in-system programming. the output voltage can be separately controlled down to 1.65v through the vccq supply pin. this device can operate in the asynchronous or page read mode. to increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. the end of a program or an erase cycle is detected by data polling or the toggle bit. the vpp pin provides data protection and faster programming and erase times. when the v pp input is below 0.8v, the program and erase functions are inhibited. when v pp is at 1.65v or above, normal program and erase operations can be performed. with v pp at 12.0v, the program and erase operations are accelerated. with v pp at 12v, a six-byte command (enter single pulse program mode) to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. after entering the six-byte code, only single pulses on the write control lines are required for writing into the device. this mode (single pulse word program) is exited by powering down the device, by taking the reset pin to gnd or by a high-to-low transition on the v pp input. erase, erase suspend/resume, program suspend/resume and read reset commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not rec- ommended that the six-byte code reside in the software of the final product but only exist in external programming code. 64-megabit (4m x 16) page mode 2.7-volt flash memory at49bv640 at49bv640t rev. 3366b?flash?8/03
2 at49bv640(t) 3366b?flash?8/03 pin configurations at49bv640(t) cbga top view at49bv640(t) tsop top view type 1 pin name pin function i/o0 - i/o15 data inputs/outputs a0 - a21 addresses ce chip enable oe output enable we write enable reset reset wp write protect vpp write protection and power supply for accelerated program/erase operations vccq output power supply a b c d e f 1 234567 a13 a14 a15 a16 vccq gnd a11 a10 a12 i/o14 i/o15 i/o7 a8 we a9 i/o5 i/o6 i/o13 vpp rst a21 i/o11 i/o12 i/o4 wp a18 a20 i/o2 i/o3 vcc a19 a17 a6 i/o8 i/o9 i/o10 a7 a5 a3 ce i/o0 i/o1 a4 a2 a1 a0 gnd oe 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a21 a20 we reset vpp wp a19 a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 vccq gnd i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe gnd ce a0
3 at49bv640(t) 3366b?flash?8/03 device operation command sequences: the device powers on in the read mode. command sequences are used to place the device in other operating modes such as program and erase. after the completion of a program or an erase cycle, the device enters the read mode. the command sequences are written by applying a low pulse on the we input with ce low and oe high or by applying a low-going pulse on the ce input with we low and oe high. the address is latched on the falling edge of the we or ce pulse which- ever occurs first. valid data is latched on the rising edge of the we or the ce pulse, whichever occurs first. the addresses used in the command sequences are not affected by entering the command sequences. asynchronous read: the at49bv640(t) is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in pre- venting bus contention. page read: the page read operation of the device is controlled by ce and oe inputs. the page size is four words. the first word access of the page read is the same as the asynchronous read. the first word is read at an asynchronous speed of 80 ns. once the first word is read, toggling a0 and a1 will result in subsequent reads within the page being output at a speed of 20 ns. the page read diagram is shown on page 20. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset pin halts the present device operation and puts the outputs of the device in a high-impedance state. when a high level is reasserted on the reset pin, the device returns to read or standby mode, depending upon the state of the control pins. erase: before a word can be reprogrammed it must be erased. the erased state of the memory bits is a logical ?1?. the entire memory can be erased by using the chip erase command or individual sectors can be erased by using the sector erase command. chip erase: chip erase is a six-bus cycle operation. the automatic erase begins on the rising edge of the last we pulse. chip erase does not alter the data of the protected sectors. after the full chip erase the device will return back to the read mode. the hard- ware reset during chip erase will stop the erase but the data will be of unknown state. any command during chip erase except erase suspend will be ignored. sector erase: as an alternative to a full chip erase, the device is organized into multiple sectors that can be individually erased. the sector erase command is a six-bus cycle operation. the sector whose address is valid at the sixth falling edge of we will be erased provided the given sector has not been protected. word programming: the device is programmed on a word-by-word basis. pro- gramming is accomplished via the internal device command register and is a four-bus cycle operation. the programming address and data are latched in the fourth cycle. the device will automatically generate the requ ired internal progr amming pulses. please note that a ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. flexible sector protection: the at49bv640(t) offers two sector protection modes, the softlock and the hardlock. the softlock mode is optimized as sector protec- tion for sectors whose content changes fr equently. the hardlock protection mode is recommended for sectors whose content changes infrequently. once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased
4 at49bv640(t) 3366b?flash?8/03 or programmed. each sector can be independently programmed for either the softlock or hardlock sector protection mode. at power-up and reset, all sectors have their soft- lock protection mode enabled. softlock and unlock: the softlock protection mode can be disabled by issuing a two-bus cycle unlock command to the selected sector. once a sector is unlocked, its contents can be erased or programmed. to enable the softlock protection mode, a six- bus cycle softlock command must be issued to the selected sector. hardlock and write protect (wp ): the hardlock sector protection mode oper- ates in conjunction with the write protection (wp ) pin. the hardlock sector protection mode can be enabled by issuing a six-bus cycle hardlock software command to the selected sector. the state of the write protect pin affects whether the hardlock protec- tion mode can be overridden. when the wp pin is low and the hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. when the wp pin is high, the hardlock protection mode is overridden and the sector can be unlocked via the unlock command. to disable the hardlock sector protection mode, the chip must be either reset or power cycled. sector protection detection: a software method is available to determine if the sector protection softlock or hardlock features are enabled. when the device is in the software product identification mode (see software product identification entry and exit sections) a read from the i/o0 and i/o1 at address location 00002h within a sector will show if the sector is unlocked, softlocked, or hardlocked. table 1. hardlock and softlock protection configurations in conjunction with wp v pp wp hard lock soft lock erase/ prog allowed? comments v cc /5v 0 0 0 yes no sector is locked v cc /5v 0 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc /5v 0 1 1 no hardlock protection mode is enabled. the sector cannot be unlocked. v cc /5v 1 0 0 yes no sector is locked. v cc /5v 1 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc /5v 1 1 0 yes hardlock protection mode is overridden and the sector is not locked. v cc /5v 1 1 1 no hardlock protection mode is overridden and the sector can be unlocked via the unlock command. v il x x x no erase and program operations cannot be performed.
5 at49bv640(t) 3366b?flash?8/03 program/erase status: the device provides several bits to determine the status of a program or erase operation: i/o2, i/o3, i/o5, i/o6, and i/o7. all other status bits are don?t care. the table 4 on page 25 and the following four sections describe the function of these bits. to provide greater flexibility for system designers, the at49bv640(t) con- tains a programmable configuration register. the configuration register allows the user to specify the status bit operation. the configuration register can be set to one of two dif- ferent values, ?00? or ?01?. if the configuration register is set to ?00?, the part will automatically return to the read mode after a successful program or erase operation. if the configuration register is set to a ?01?, a product id exit command must be given after a successful program or erase operation before the part will return to the read mode. it is important to note that whether the configuration register is set to a ?00? or to a ?01?, any unsuccessful program or erase operati on requires using the product id exit com- mand to return the device to read mode. the default value (after power-up) for the configuration register is ?00?. using the four-bus cycle set configuration register com- mand as shown in the command definition table on page 11, the value of the configuration register can be changed. voltages applied to the reset pin will not alter the value of the configuration register. the value of the configuration register will affect the operation of the i/o7 status bit as described below. data polling: the at49bv640(t) features data polling to indicate the end of a pro- gram cycle. if the status configuration register is set to a ?00?, during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip erase or sector erase operation, an attempt to read the device will give a ?0? on i/o7. once the program or erase cycle has com- pleted, true data will be read from the device. data polling may begin at any time during the program cycle. please see table 3 on page 10 for more details. if the status bit configuration register is set to a ?01?, the i/o7 status bit will be low while the device is actively programming or erasing data. i/o7 will go high when the device has completed a program or erase operation. once i/o7 has gone high, status informa- tion on the other pins can be checked. the data polling status bit must be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 2 and 3. toggle bit: in addition to data polling, the at49bv640(t) provides another method for determining the end of a program or erase cycle. during a program or erase opera- tion, successive attempts to read data from the memory will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a pro- gram cycle. please see table 3 on page 10 for more details. the toggle bit status bit should be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 4 and 5 on page 9. table 2. sector protection status i/o1 i/o0 sector protection status 0 0 sector not locked 0 1 softlock enabled 1 0 hardlock enabled 1 1 both hardlock and softlock enabled
6 at49bv640(t) 3366b?flash?8/03 erase/program status bit: the device offers a status bit on i/o5 that indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ?1?, the device is unable to verify that an erase or a word pro- gram operation has been successfully performed. the device may also output a ?1? on i/o5 if the system tries to program a ?1? to a location that was previously programmed to a ?0?. only an erase operation can change a ?0? back to a ?1?. if a program (sector erase) command is issued to a protected sector, the protected sector will not be pro- grammed (erased). the device will go to a status read mode and the i/o5 status bit will be set high, indicating the program (erase) operation did not complete as requested. once the erase/program status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. the erase/program status bit is a ?0? while the erase or program operation is still in progress. please see table 3 on page 10 for more details. v pp status bit: the at49bv640(t) provides a status bit on i/o3 that provides infor- mation regarding the voltage level of the vpp pin. during a program or erase operation, if the voltage on the vpp pin is not high enough to perform the desired operation suc- cessfully, the i/o3 status bit will be a ?1?. once the v pp status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. on the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the v pp status bit will output a ?0?. please see table 3 on page 10 for more details. erase suspend/erase resume: the erase suspend command allows the sys- tem to interrupt a sector erase operation and then program or read data from a different sector. after the erase suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. the system can then read data or pro- gram data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command, which does require the sector address. the device also supports an erase suspend during a com- plete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is protected. the command sequence for a chip erase suspend and a sector erase suspend are the same. program suspend/program resume: the program suspend command allows the system to interrupt a programming oper ation and then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. after the program- ming operation has been suspended, the system can then read from any other word within the device. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume com- mand. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. 128-bit protection register: the at49bv640(t) contains a 128-bit register that can be used for security purposes in system design. the protection register is divided into two 64-bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. to program block b in the protection register, the four-bus cycle program protection register command must be used as shown in the command definition in hex table on page 11. to lock out block b, the four-bus cycle lock protection register command must be used as shown in the command definition in
7 at49bv640(t) 3366b?flash?8/03 hex table. data bit d1 must be zero during the fourth bus cycle. all other data bits during the fourth bus cycle are don?t cares. to determine whether block b is locked out, the product id entry command is given followed by a read operation from address 80h. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be repro- grammed. please see the protection register addressing table on page 12 for the address locations in the protection register. to read the protection register, the product id entry command is given followed by a normal read operation from an address within the protection register. after determining whether block b is protected or not or reading the protection register, the product id exit command must be given prior to performing any other operation. cfi: common flash interface (cfi) is a published, standardized data structure that may be read from a flash device. cfi allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. cfi is used to allow the system to learn how to inter- face to the flash device most optimally. the two primary benefits of using cfi are ease of upgrading and second source availability. the command to enter the cfi query mode is a one-bus cycle command which requires writing data 98h to address 55h. the cfi query command can be written when the device is ready to read data or can also be written when the part is in the product id mode. once in the cfi query mode, the system can read cfi data at the addresses given in table 4 on page 25. to exit the cfi query mode, the product id exit command must be given. if the cfi query command is given while the part is in the product id mode, then the product id exit command must first be given to return the part to the product id mode. once in the product id mode, it will be necessary to give another product id exit command to return the part to the read mode. hardware data protection: hardware features protect against inadvertent pro- grams to the at49bv640(t) in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time-out 10 ms (typical) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. (e) v pp is less than v ilpp . input levels: while operating with a 2.7v to 3.6v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can be driven from 0 to v ccq + 0.6v. output levels: for the at49bv640(t), output high levels are equal to v ccq - 0.1v (not v cc ). for 2.7v to 3.6v output levels, v ccq must be tied to v cc .
8 at49bv640(t) 3366b?flash?8/03 figure 1. data polling algorithm (configuration register = 00) notes: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ?1? because i/o7 may change simultaneously with i/o5. start read i/o7 - i/o0 addr = va i/o7 = data? i/o3, i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode figure 2. data polling algorithm (configuration register = 01) note: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. start read i/o7 - i/o0 addr = va i/o7 = 1? i/o3, i/o5 = 1? program/erase operation not successful, write product id exit command no no yes yes program/erase operation successful, write product id exit command
9 at49bv640(t) 3366b?flash?8/03 figure 3. toggle bit algorithm (configuration register = 00) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, device in read mode no no no yes yes yes figure 4. toggle bit algorithm (configuration register = 01) note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
10 at49bv640(t) 3366b?flash?8/03 notes: 1. i/o5 switches to a ?1? when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. i/o3 switches to a ?1? when the v pp level is not high enough to successfully perform program and erase operations. table 3. status bit table status bit i/o7 i/o7 i/o6 i/o5 (1) i/o3 (2) i/o2 configuration register 00 01 00/01 00/01 00/01 00/01 programming i/o7 0 toggle 0 0 1 erasing 0 0 toggle 0 0 toggle erase suspended & read erasing sector 11100t o g g l e erase suspended & read non-erasing sector data data data data data data erase suspended & program non-erasing sector i/o7 0 toggle 0 0 toggle erase suspended & program suspended and reading from non-suspended sectors data data data data data data program suspended & read non-suspended word data data data data data data
11 at49bv640(t) 3366b?flash?8/03 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (hex). the address format in ea ch bus cycle is as follows: a11 - a0 (hex), a11 - a21 (don?t care). 2. since a11 is a don?t care, aaa can be replaced with 2aa. 3. either one of the product id exit commands can be used. 4. sa = sector address. any word address within a sector can be used to designate the sector address (see pages 13 - 17 for deta ils). 5. once a sector is in the hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled. 6. if data bit d1 is ?0?, block b is locked. if data bit d1 is ?1?, block b can be reprogrammed. 7. the default state (after power-up) of the configuration register is ?00?. command definition in (hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4) 30 word program 4 555 aa aaa 55 555 a0 addr d in enter single-pulse program mode 6 555 aa aaa 55 555 80 555 aa aaa 55 555 a0 single-pulse word program mode 1addrd in sector softlock 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4) 40 sector unlock 2 555 aa sa (4) 70 sector hardlock 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (4)(5) 60 erase/program suspend 1 xxx b0 erase/program resume 1 sa (4) 30 product id entry 3 555 aa aaa 55 555 90 product id exit (3) 3 555 aa aaa 55 555 f0 product id exit (3) 1 xxx fx program protection register ? block b 4 555 aa aaa 55 555 c0 addr d in lock protection register ? block b 4 555 aa aaa 55 555 c0 080 x0 status of block b protection 4 555 aa aaa 55 555 90 80 d out (6) set configuration register 4 555 aa aaa 55 555 e0 xxx 00/01 (7) cfi query 1 x55 98
12 at49bv640(t) 3366b?flash?8/03 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a21 - a8 = 0. absolute maximum ratings* temperature under bias ................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages except v pp (including nc pins) with respect to ground ...................................-0.6v to +6.25v v pp input voltage with respect to ground ......................................... 0v to 13.0v all output voltages with respect to ground ...........................-0.6v to v ccq + 0.6v protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0factorya10000001 1factorya10000010 2factorya10000011 3factorya10000100 4userb10000101 5userb10000110 6userb10000111 7userb10001000
13 at49bv640(t) 3366b?flash?8/03 memory organization C at49bv640 sector size (words) x16 address range (a21 - a0) sa0 4k 00000 - 00fff sa1 4k 01000 - 01fff sa2 4k 02000 - 02fff sa3 4k 03000 - 03fff sa4 4k 04000 - 04fff sa5 4k 05000 - 05fff sa6 4k 06000 - 06fff sa7 4k 07000 - 07fff sa8 32k 08000 - 0ffff sa9 32k 10000 - 17fff sa10 32k 18000 - 1ffff sa11 32k 20000 - 27fff sa12 32k 28000 - 2ffff sa13 32k 30000 - 37fff sa14 32k 38000 - 3ffff sa15 32k 40000 - 47fff sa16 32k 48000 - 4ffff sa17 32k 50000 - 57fff sa18 32k 58000 - 5ffff sa19 32k 60000 - 67fff sa20 32k 68000 - 6ffff sa21 32k 70000 - 77fff sa22 32k 78000 - 7ffff sa23 32k 80000 - 87fff sa24 32k 88000 - 8ffff sa25 32k 90000 - 97fff sa26 32k 98000 - 9ffff sa27 32k a0000 - a7fff sa28 32k a8000 - affff sa29 32k b0000 - b7fff sa30 32k b8000 - bffff sa31 32k c0000 - c7fff sa32 32k c8000 - cffff sa33 32k d0000 - d7fff sa34 32k d8000 - dffff sa35 32k e0000 - e7fff sa36 32k e8000 - effff sa37 32k f0000 - f7fff sa38 32k f8000 - fffff sa39 32k 100000 - 107fff sa40 32k 108000 - 10ffff sa41 32k 110000 - 117fff sa42 32k 118000 - 11ffff sa43 32k 120000 - 127fff sa44 32k 128000 - 12ffff sa45 32k 130000 - 137fff sa46 32k 138000 - 13ffff sa47 32k 140000 - 147fff sa48 32k 148000 - 14ffff sa49 32k 150000 - 157fff sa50 32k 158000 - 15ffff sa51 32k 160000 - 167fff sa52 32k 168000 - 16ffff sa53 32k 170000 - 177fff sa54 32k 178000 - 17ffff sa55 32k 180000 - 187fff sa56 32k 188000 - 18ffff sa57 32k 190000 - 197fff sa58 32k 198000 - 19ffff sa59 32k 1a0000 - 1a7fff sa60 32k 1a8000 - 1affff sa61 32k 1b0000 - 1b7fff sa62 32k 1b8000 - 1bffff sa63 32k 1c0000 - 1c7fff sa64 32k 1c8000 - 1cffff sa65 32k 1d0000 - 1d7fff sa66 32k 1d8000 - 1dffff sa67 32k 1e0000 - 1e7fff sa68 32k 1e8000 - 1effff sa69 32k 1f0000 - 1f7fff sa70 32k 1f8000 - 1fffff sa71 32k 200000 - 207fff sa72 32k 208000 - 20ffff sa73 32k 210000 - 217fff sa74 32k 218000 - 21ffff sa75 32k 220000 - 227fff sa76 32k 228000 - 22ffff sa77 32k 230000 - 237fff sa78 32k 238000 - 23ffff sa79 32k 240000 - 247fff sa80 32k 248000 - 24ffff sa81 32k 250000 - 257fff sa82 32k 258000 - 25ffff sa83 32k 260000 - 267fff sa84 32k 268000 - 26ffff sa85 32k 270000 - 277fff sa86 32k 278000 - 27ffff sa87 32k 280000 - 287fff sa88 32k 288000 - 28ffff sa89 32k 290000 - 297fff memory organization C at49bv640 (continued) sector size (words) x16 address range (a21 - a0)
14 at49bv640(t) 3366b?flash?8/03 sa90 32k 298000 - 29ffff sa91 32k 2a0000 - 2a7fff sa92 32k 2a8000 - 2affff sa93 32k 2b0000 - 2b7fff sa94 32k 2b8000 - 2bffff sa95 32k 2c0000 - 2c7fff sa96 32k 2c8000 - 2cffff sa97 32k 2d0000 - 2d7fff sa98 32k 2d8000 - 2dffff sa99 32k 2e0000 - 2e7fff sa100 32k 2e8000 - 2effff sa101 32k 2f0000 - 2f7fff sa102 32k 2f8000 - 2fffff sa103 32k 300000 - 307fff sa104 32k 308000 - 30ffff sa105 32k 310000 - 317fff sa106 32k 318000 - 31ffff sa107 32k 320000 - 327fff sa108 32k 328000 - 32ffff sa109 32k 330000 - 337fff sa110 32k 338000 - 33ffff sa111 32k 340000 - 347fff sa112 32k 348000 - 34ffff memory organization C at49bv640 (continued) sector size (words) x16 address range (a21 - a0) sa113 32k 350000 - 357fff sa114 32k 358000 - 35ffff sa115 32k 360000 - 367fff sa116 32k 368000 - 36ffff sa117 32k 370000 - 377fff sa118 32k 378000 - 37ffff sa119 32k 380000 - 387fff sa120 32k 388000 - 38ffff sa121 32k 390000 - 397fff sa122 32k 398000 - 39ffff sa123 32k 3a0000 - 3a7fff sa124 32k 3a8000 - 3affff sa125 32k 3b0000 - 3b7fff sa126 32k 3b8000 - 3bffff sa127 32k 3c0000 - 3c7fff sa128 32k 3c8000 - 3cffff sa129 32k 3d0000 - 3d7fff sa130 32k 3d8000 - 3dffff sa131 32k 3e0000 - 3e7fff sa132 32k 3e8000 - 3effff sa133 32k 3f0000 - 3f7fff sa134 32k 3f8000 - 3fffff memory organization C at49bv640 (continued) sector size (words) x16 address range (a21 - a0)
15 at49bv640(t) 3366b?flash?8/03 memory organization C at49bv640t sector size (words) x16 address range (a21 - a0) sa0 32k 00000 - 07fff sa1 32k 08000 - 0ffff sa2 32k 10000 - 17fff sa3 32k 18000 - 1ffff sa4 32k 20000 - 27fff sa5 32k 28000 - 2ffff sa6 32k 30000 - 37fff sa7 32k 38000 - 3ffff sa8 32k 40000 - 47fff sa9 32k 48000 - 4ffff sa10 32k 50000 - 57fff sa11 32k 58000 - 5ffff sa12 32k 60000 - 67fff sa13 32k 68000 - 6ffff sa14 32k 70000 - 77fff sa15 32k 78000 - 7ffff sa16 32k 80000 - 87fff sa17 32k 88000 - 8ffff sa18 32k 90000 - 97fff sa19 32k 98000 - 9ffff sa20 32k a0000 - a7fff sa21 32k a8000 - affff sa22 32k b0000 - b7fff sa23 32k b8000 - bffff sa24 32k c0000 - c7fff sa25 32k c8000 - cffff sa26 32k d0000 - d7fff sa27 32k d8000 - dffff sa28 32k e0000 - e7fff sa29 32k e8000 - effff sa30 32k f0000 - f7fff sa31 32k f8000 - fffff sa32 32k 100000 - 107fff sa33 32k 108000 - 10ffff sa34 32k 110000 - 117fff sa35 32k 118000 - 11ffff sa36 32k 120000 - 127fff sa37 32k 128000 - 12ffff sa38 32k 130000 - 137fff sa39 32k 138000 - 13ffff sa40 32k 140000 - 147fff sa41 32k 148000 - 14ffff sa42 32k 150000 - 157fff sa43 32k 158000 - 15ffff sa44 32k 160000 - 167fff sa45 32k 168000 - 16ffff sa46 32k 170000 - 177fff sa47 32k 178000 - 17ffff sa48 32k 180000 - 187fff sa49 32k 188000 - 18ffff sa50 32k 190000 - 197fff sa51 32k 198000 - 19ffff sa52 32k 1a0000 - 1a7fff sa53 32k 1a8000 - 1affff sa54 32k 1b0000 - 1b7fff sa55 32k 1b8000 - 1bffff sa56 32k 1c0000 - 1c7fff sa57 32k 1c8000 - 1cffff sa58 32k 1d0000 - 1d7fff sa59 32k 1d8000 - 1dffff sa60 32k 1e0000 - 1e7fff sa61 32k 1e8000 - 1effff sa62 32k 1f0000 - 1f7fff sa63 32k 1f8000 - 1fffff sa64 32k 200000 - 207fff sa65 32k 208000 - 20ffff sa66 32k 210000 - 217fff sa67 32k 218000 - 21ffff sa68 32k 220000 - 227fff sa69 32k 228000 - 22ffff sa70 32k 230000 - 237fff sa71 32k 238000 - 23ffff sa72 32k 240000 - 247fff sa73 32k 248000 - 24ffff sa74 32k 250000 - 257fff sa75 32k 258000 - 25ffff sa76 32k 260000 - 267fff sa77 32k 268000 - 26ffff sa78 32k 270000 - 277fff sa79 32k 278000 - 27ffff sa80 32k 280000 - 287fff sa81 32k 288000 - 28ffff sa82 32k 290000 - 297fff sa83 32k 298000 -29ffff sa84 32k 2a0000 - 2a7fff sa85 32k 2a8000 - 2affff sa86 32k 2b0000 - 2b7fff sa87 32k 2b8000 - 2bffff sa88 32k 2c0000 - 2c7fff sa89 32k 2c8000 - 2cffff memory organization C at49bv640t (continued) sector size (words) x16 address range (a21 - a0)
16 at49bv640(t) 3366b?flash?8/03 sa90 32k 2d0000 - 2d7fff sa91 32k 2d8000 - 2dffff sa92 32k 2e0000 - 2e7fff sa93 32k 2e8000 - 2effff sa94 32k 2f0000 - 2f7fff sa95 32k 2f8000 - 2fffff sa96 32k 300000 - 307fff sa97 32k 308000 - 30ffff sa98 32k 310000 - 317fff sa99 32k 318000 - 31ffff sa100 32k 320000 - 327fff sa101 32k 328000 - 32ffff sa102 32k 330000 - 337fff sa103 32k 338000 - 33ffff sa104 32k 340000 - 347fff sa105 32k 348000 - 34ffff sa106 32k 350000 - 357fff sa107 32k 358000 - 35ffff sa108 32k 360000 - 367fff sa109 32k 368000 - 36ffff sa110 32k 370000 - 377fff sa111 32k 378000 - 37ffff sa112 32k 380000 - 387fff memory organization C at49bv640t (continued) sector size (words) x16 address range (a21 - a0) sa113 32k 388000 - 38ffff sa114 32k 390000 - 397fff sa115 32k 398000 - 39ffff sa116 32k 3a0000 - 3a7fff sa117 32k 3a8000 - 3affff sa118 32k 3b0000 - 3b7fff sa119 32k 3b8000 - 3bffff sa120 32k 3c0000 - 3c7fff sa121 32k 3c8000 - 3cffff sa122 32k 3d0000 - 3d7fff sa123 32k 3d8000 - 3dffff sa124 32k 3e0000 - 3e7fff sa125 32k 3e8000 - 3effff sa126 32k 3f0000 - 3f7fff sa127 4k 3f8000 - 3f8fff sa128 4k 3f9000 - 3f9fff sa129 4k 3fa000 - 3fafff sa130 4k 3fb000 - 3fbfff sa131 4k 3fc000 - 3fcfff sa132 4k 3fd000 - 3fdfff sa133 4k 3fe000 - 3fefff sa134 4k 3ff000 - 3fffff memory organization C at49bv640t (continued) sector size (words) x16 address range (a21 - a0)
17 at49bv640(t) 3366b?flash?8/03 notes: 1. x can be vil or vih. 2. refer to ac programming waveforms. 3. manufacturer code: 001fh; device code: 00d6h - at49bv640; 00d2h - at49bv640t. 4. see details under ?software product identification entry/exit? on page 24. 5. the vpp pin can be tied to v cc . for faster program/erase operations, v pp can be set to 12.0v 0.5v. 6. v ihpp (min) = 1.65v. 7. v ilpp (max) = 0.8v. dc and ac operating range at49bv640(t) - 70 at49bv640(t) - 85 operating temperature (case) industrial -40c - 85c -40c - 85c v cc power supply 2.7v - 3.6v 2.7v - 3.6v operating modes mode ce oe we reset v pp (5) ai i/o read v il v il v ih v ih xa i d out burst read v il v il v ih v ih xa i d out program/erase (3) v il v ih v il v ih v ihpp (6) ai d in standby/program inhibit v ih x (1) xv ih xx h i g h z program inhibit xxv ih v ih x xv il xv ih x xxx x v ilpp (7) output disable x v ih xv ih xh i g h z reset xxx v il xx h i g h z product identification software (4) v ih a0 = v il , a1 - a21 = v il manufacturer code (3) a0 = v ih , a1 - a21 = v il device code (3)
18 at49bv640(t) 3366b?flash?8/03 note: 1. in the erase mode, i cc is 30 ma. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 1 a i lo output leakage current v i/o = 0v to v cc 1 a i sb1 v cc standby current cmos ce = v ccq - 0.3v to v cc 10 a i cc (1) v cc active current f = 5 mhz; i out = 0 ma 30 ma i ccre v cc read while erase current f = 5 mhz; i out = 0 ma 50 ma i ccrw v cc read while write current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.6 v v ih input high voltage v ccq - 0.6 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -100 a; v ccq = 1.65v - 2.2v v ccq - 0.1 v i oh = -400 a; v ccq = 2.7v - 3.1v 2.4 ac driving levels 2.0v 0.6v 1.5v ac measurement level v 1.8k output pin 30 pf 1.3k ccq pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 46 p f v in = 0v c out 81 2 p f v out = 0v
19 at49bv640(t) 3366b?flash?8/03 asynchronous read cycle waveform (1)(2)(3) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). ac asynchronous read timing characteristics symbol parameter at49bv640(t)-70 at49bv640(t)-85 units min max min max t acc access, address to data valid 70 85 ns t ce access, ce to data valid 70 85 ns t oe oe to data valid 20 20 ns t df ce , oe high to data float 25 25 ns t ro reset to output delay 150 150 ns output valid i/o0 - i/o15 high z reset oe toe tce address valid tdf toh tacc tro ce a0 - a21 trc
20 at49bv640(t) 3366b?flash?8/03 page read cycle waveform ac asynchronous read timing characteristics symbol parameter at49bv640(t)-70 at49bv640(t)-85 units min max min max t acc access, address to data valid 70 85 ns t ce access, ce to data valid 70 85 ns t oe oe to data valid 20 20 ns t df ce , oe high to data float 25 25 ns t ro reset to output delay 150 150 ns t pa a page address access time 20 20 ns t ce t acc t df t df data valid ce i/o0-i/o15 a2 -a21 oe t oe reset t ro t acc a0 -a1 t pa a
21 at49bv640(t) 3366b?flash?8/03 ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min max units t as address setup time to we and ce low 0 ns t ah address hold time 20 ns t ds data setup time 20 ns t dh data hold time 0 ns t wp ce or we low pulse width 35 ns t wph ce or we high pulse width 25 ns t ds t ah t dh t wp data valid ce i/o0-i/o15 a0 -a21 we t as t ds t dh t wp data valid ce i/o0-i/o15 a0 -a21 we t as t ah
22 at49bv640(t) 3366b?flash?8/03 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for sector erase, the address depends on what sector is to be erased. (see note 4 under command definitions on page 11.) 3. for chip erase, the data should be xx10h and for sector erase, the data should be xx30h 4. the waveforms shown above use the we controlled ac word load waveforms. program cycle characteristics symbol parameter min typ max units t bp word programming time (v pp = v cc )2 2 s t bpvpp word programming time (v pp > 11.5v) 10 s t sec1 sector erase cycle time (4k word sectors) 100 ms t sec2 sector erase cycle time (32k word sectors) 500 ms t es erase suspend time 15 s t ps program suspend time 10 s input data xxaa ce we i/o0 -i/o15 xx55 xxa0 a0 -a21 addr 555 aaa 555 oe (1) oe (1) xxaa xxaa ce we i/o0 -i/o15 xx55 xx80 a0 -a21 555 555 aaa 555 xx55 note3 aaa note2
23 at49bv640(t) 3366b?flash?8/03 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec on page 19. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec on page 19. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns a0-a21 we ce oe i/o7 toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns
24 at49bv640(t) 3366b?flash?8/03 software product identification entry (1) load data aa to address 555 load data 55 to address aaa load data 90 to address 555 enter product identification mode (2)(3)(5) software product identification exit (1)(6) load data aa to address 555 load data 55 to address aaa load data f0 to address 555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) notes: 1. data format: i/o15 - i/o8 (don?t care); i/o7 - i/o0 (h ex) address format: a11 - a0 (hex); a12 - a21 (don?t care). 2. a1 - a21 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 001fh device code: 00d6h - at49bv640; 00d2h - at49bv640t. 6. either one of the product id exit commands can be used.
25 at49bv640(t) 3366b?flash?8/03 table 4. common flash interface definition for at49bv640(t) address data comments 10h 0051h ?q? 11h 0052h ?r? 12h 0059h ?y? 13h 0002h 14h 0000h 15h 0041h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1ah 0000h 1bh 0027h vcc min write/erase 1ch 0031h vcc max write/erase 1dh 00b5h vpp min voltage 1eh 00c5h vpp max voltage 1fh 0004h typ word write ? 16 s 20h 0000h 21h 0009h typ block erase ? 500 ms 22h 0010h typ chip erase ? 64,300 ms 23h 0004h max word write/typ time 24h 0000h n/a 25h 0003h max block erase/typ block erase 26h 0003h max chip erase/ typ chip erase 27h 0017h device size 28h 0001h x16 device 29h 0000h x16 device 2ah 0000h multiple byte write not supported 2bh 0000h multiple byte write not supported 2ch 0002h 2 regions, x = 2 2dh 007eh 64k bytes, y = 126 2eh 0000h 64k bytes, y = 126 2fh 0000h 64k bytes, z = 256 30h 0001h 64k bytes, z = 256 31h 0007h 8k bytes, y = 7 32h 0000h 8k bytes, y = 7 33h 0020h 8k bytes, z = 32 34h 0000h 8k bytes, z = 32
26 at49bv640(t) 3366b?flash?8/03 vendor specific extended query 41h 0050h ?p? 42h 0052h ?r? 43h 0049h ?i? 44h 0031h major version number, ascii 45h 0030h minor version number, ascii 46h 00a7h bit 0 ? chip erase supported, 0 ? no, 1 ? yes bit 1 ? erase suspend supported, 0 ? no, 1 ? yes bit 2 ? program suspend supported, 0 ? no, 1 ? yes bit 3 ? simultaneous operations supported, 0 ? no, 1 ? yes bit 4 ? burst mode read supported, 0 ? no, 1 ? yes bit 5 ? page mode read supported, 0 ? no, 1 ? yes bit 6 ? queued erase supported, 0 ? no, 1 ? yes bit 7 ? protection bits supported, 0 ? no, 1 ? yes 47h 0000h at49bv640t or 0001h at49bv640 bit 0 ? top (?0?) or bottom (?1?) boot block device undefined bits are ?0? 48h 0000h bit 0 ? 4 word linear burst with wrap around, 0 ? no, 1 ? yes bit 1 ? 8 word linear burst with wrap around, 0 ? no, 1 ? yes bit 2 ? continuos burst, 0 ? no, 1 ? yes undefined bits are ?0? 49h 0001h bit 0 ? 4 word page, 0 ? no, 1 ? yes bit 1 ? 8 word page, 0 ? no, 1 ? yes undefined bits are ?0? 4ah 0080h location of protection register lock byte, the section's first byte 4bh 0003h # of bytes in the factory prog section of prot register ? 2*n 4ch 0003h # of bytes in the user prog section of prot register ? 2*n table 4. common flash interface definition for at49bv640(t) (continued) address data comments
27 at49bv640(t) 3366b?flash?8/03 at49bv640(t) ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 30 0.01 at49bv640-70ti at49bv640-70ci 48t 48c18 industrial (-40 to 85 c) 85 30 0.01 AT49BV640-85TI at49bv640-85ci 48t 48c18 industrial (-40 to 85 c) 70 30 0.01 at49bv640t-70ti at49bv640t-70ci 48t 48c18 industrial (-40 to 85 c) 85 30 0.01 at49bv640t-85ti at49bv640t-85ci 48t 48c18 industrial (-40 to 85 c) package type 48c18 48-ball, plastic chip-size ball grid array package (cbga) 48t 48-lead, plastic thin small outline package (tsop)
28 at49bv640(t) 3366b?flash?8/03 packaging information C at49bv640(t) 48c18 C cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 48c18, 48-ball (8 x 6 array),0.75 mm pitch, 8.0 x 11.0 x 1.0 mm chip-scale ball grid array package (cbga) a 48c18 08/8/03 a1 ball id a b c d e f 7 65432 1 d e e1 e 1.375 ref a1 ball corner 3.625 ref d1 8 a a1 common dimensions (unit of measure = mm) symbol min nom max note e 7.90 8.00 8.10 e1 5.25 typ d 10.90 11.00 11.10 d1 3.75 typ a ? ? 1.0 a1 0.21 ? ? e 0.75 bsc ? b 0.35 typ bottom view ? b top view side view
29 at49bv640(t) 3366b?flash?8/03 packaging information C at49bv640(t) 48t C tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 48t , 48-lead (12 x 20 mm package) plastic thin small outline package, type i (tsop) b 48t 10/18/01 pin 1 0o ~ 8o d1 d pin 1 identifier b e e a a2 c l gage plane seating plane l1 a1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation dd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 11.90 12.00 12.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
printed on recycled paper. 3366b?flash?8/03 xm disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel c orporation 2 003 . al l r ights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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